IET Renewable Power Generation
Research Article
Performance evaluation of an asymmetrical
reduced switched multi-level inverter for a
grid-connected PV system
ISSN 1752-1416
Received on 31st October 2016
Revised 21st August 2017
Accepted on 8th September 2017
E-First on 24th November 2017
doi: 10.1049/iet-rpg.2016.0895
http://www.ietdl.org
Madan Kumar Das1, Kartick Chandra Jana1 , Akanksha Sinha1
1Electrical Engineering, Indian Institute of Technology (Indian School of Mines), Dhanbad 826004, India
E-mail: kartick_jana@yahoo.com
Abstract: This study presents the performance analysis of a new asymmetrical multi-level inverter using reduced number of
switches for a single-phase grid-tied photovoltaic (PV) system. The solar PV panels of unequal power rating are connected in an
appropriate manner to obtain the DC link voltages of suitable ratio for an asymmetrical cascaded multi-level inverter. The PV
power, voltages as well as the current injected into the grid have been controlled using the separate maximum power point
tracking, voltage controllers and a current controlled technique to achieve the maximum power with sinusoidal current with a
unity power factor. The variations of DC link voltages, inverter voltage and injected grid current are simulated and are
experimentally verified under the variable irradiation as well as grid voltage fluctuation. The simulation and the corresponding
hardware results of the proposed reduced switch asymmetrical seven-level inverter for a low-power residential grid-tied PV
system is also presented.
1 Introduction
Solar photovoltaic (PV) systems with multi-level inverters (MLIs)
are increasingly used for grid-tied and stand-alone applications [1–
3]. Though, in stand-alone and grid-tied PV systems, commonly
the conventional two- and three-level inverters are used [1, 2].
However, they suffer from high total harmonic distortion (THD) of
line current and high dv/dt stress on inverter switches. Moreover, to
minimise the harmonics and THD in the inverter current, the pulse
width modulation (PWM) switching frequency required is
generally very high, hence the switching losses become high. There
are several MLI topologies existing for the grid-tied PV systems,
such as diode clamped inverter [3], capacitor clamped inverter [4]
and cascaded H-bridge (CHB) MLI [5–7] and hybrid MLI [8–11].
The symmetric cascaded MLIs are becoming popular due to its
modularity in design, possibility to extend the capacity as well as
the number of the voltage levels in near future. However, the
power losses of the above conventional inverters are generally
high, as more number of power switches are used for a high-level
inverter and they normally operate at higher switching frequency.
The cascaded MLIs with asymmetric configuration (voltage
sources with unequal voltage magnitude) can increase the number
of voltage levels [12, 13]. However, in the conventional cascaded
inverter, the number of switching devices are still high and
increases with the levels of the inverter.
For a solar PV system, where the energy conversion efficiency
is already limited (commercial efficiency is <20%), the
conventional MLI configurations are not becoming popular
commercially. However, the asymmetrical MLI with the reduced
number of switches can increase the inverter voltage levels further
operating at a lower switching frequency, may be considered as a
future PV inverters with improved efficiency. For a MLI with
reduced number of switches operating at comparatively lesser
switching frequency improve the efficiency of the PV inverter and
minimise the filter requirements for a grid-tied or stand-alone
applications.
Recently, several MLIs with reduced number of devices are
increasingly employed in the various applications of power
electronics [14–26]. Most of the reduced switched MLIs
configurations have the level generating parts along with polarity
generating part [18–26]. Some of the MLI topologies are only
suitable for symmetrical inverter (with equal DC link voltages)
configuration [19–21, 24, 25]. In [23], a packed U-cells based
asymmetrical MLI is proposed, which cannot operate under
symmetric source conditions. In some of the inverter
configurations, the level generating part consists of several
bidirectional switches [19–21, 24, 26], combining two switches
back to back. In [16], a cascaded switched-diode configuration is
proposed for a MLI (symmetric and asymmetric configuration)
using the controlled switches as well as several power diodes to
increase the voltage level. Though, the above MLIs have used a
lesser number of switches, however, the voltage blocking
capability of the switches in the polarity generating part is much
higher than the switches used in the level generating part of the
inverter. Several reduced switch MLIs are proposed for
symmetrical voltage sources using capacitors with equal capacitor
voltages [14]. However, the inverter with asymmetrical voltage
sources cannot generate all the voltage levels. In addition to this,
the paper demonstrated the circuit with all bi-directional switches
that increases the cost of the inverter for higher voltage levels.
The MLI with reduced number of switches for renewable
energy applications, such as PV applications have a tremendous
potential to improve the efficiency as well as the harmonics of the
grid-tied PV system. Recently, a few researchers have proposed
several less switch MLI configuration for a grid-tied PV
application [20, 27–29]. In [20], a seven-level grid-tied inverter is
proposed with a relatively lesser number of power switches and a
DC source with capacitor splitting in three equal parts are
proposed. However, no details are given regarding the capacitor
voltage balancing. A generalised cascaded MLI with lesser number
of switches is proposed for the grid-connected PV system [28] that
explained the DC link voltage balancing among several DC links.
However, the above inverters are configured for symmetrical PV
voltages only and required more number of switches. The
asymmetrical MLI for the PV application is still not reported by
any researcher.
In this paper, a reduced switch asymmetrical MLI is proposed
for a grid-tied solar PV system based on a symmetrical inverter
configuration [14]. In addition to this, the number of bi-directional
switches is also minimised in this proposed work. The paper is
organised in the following way. The operation of the proposed
reduced switch MLI is explained in Section 2. In Section 3, a grid
current control technique along with a suitable maximum power
point tracking (MPPT) [29–32] is explained. Also, the condition of
both the PV systems under non-uniform irradiance condition has
been discussed [33, 34], following to the PWM technique [35, 36]
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252
and inverter efficiency calculations [37] in Section 4 for the
proposed MLI-based grid-tied PV system. The whole power circuit
and control algorithm are simulated using Matlab/Simulink
platform and the simulation results are experimentally verified by
the hardware results as presented in Section 5. Finally, the
conclusions are presented in Section 6.
2 Asymmetrical multi-level inverter
An asymmetrical MLI with reduced number of switches for a gridtied
PV system is proposed. A 13-level asymmetrical inverter with
reduced number of switches for a grid-tied PV system is shown in
Fig. 1a. The DC link voltages of magnitude in the ratio of 1:2:3
(VDC1:VDC2:VDC3 = VDC:2VDC:3VDC) for the 13-level
asymmetrical inverter can be obtained from the solar PV array of
unequal power rating with power ratio similar to the magnitude of
the DC link voltages. The proposed reduced switch asymmetrical
MLI has been developed similar to the configuration given in [14].
However, the inverter presented in [14] is configured for the
symmetrical voltage sources only as the asymmetrical
configuration does not provide all the voltage levels. In addition to
this, the inverter in [14] used bidirectional switches only.
In this paper, an asymmetrical reduced switch MLI is developed
by selecting the suitable DC link voltage ratio and the positions of
the DC voltages in the inverter for higher voltage levels. The
proposed reduced switch asymmetric MLI consists of four
unidirectional switches (T1, T2, T3 and T4) along with a couple of
bi-directional switches such as S1, S2, S3 and S4 for a 13-level
inverter as shown in Fig. 1a. For a 13-level inverter, the ratio of the
DC link voltages can be selected as 1:2:3 and the position
(placement of sources) of the voltage sources should be chosen in
such a manner that all the possible voltage levels can be obtained
by proper triggering of the inverter switches. Table 1 shows the
switching states and the ON/OF status of all the switches of the
proposed 13-level inverter. The voltage source VDC3 has been
placed middle of the three DC links (as central DC link) as shown
in Fig. 1a to obtain the 13 voltage levels of magnitude (VDC3 +
VDC2 + VDC1), (VDC3 + VDC2), (VDC3 + VDC1), VDC3, VDC2, VDC1, 0,
−VDC1, −VDC2, −VDC3, −(VDC3 + VDC1), −(VDC3 + VDC2) and −
(VDC3 + VDC2 + VDC1) based on Table 1.
Fig. 1 Proposed grid-tied PV inverter configuration for
(a) Thirteen-level with VDC1:VDC2:VDC3 = 1:2:3, (b) Seven-level with VDC1:VDC2 = 1:2
Table 1 Switching states and ON/OF status of the 13-level inverter with VDC1:VDC2:VDC3 = VDC: 2VDC: 3VDC
Switching states (S) Switching status (ON = 1, OFF = 0) Inverter output voltage, Vab
T1 T2 T3 T4 S1 S2 S3 S4
6 1 0 0 1 0 0 0 0 VDC1 + VDC2 + VDC3 = + 6VDC
5 1 0 0 0 0 0 0 1 VDC2 + VDC3 = + 5VDC
4 0 0 0 1 1 0 0 0 VDC1 + VDC3 = + 4VDC
3 0 0 0 0 1 0 0 1 VDC3 = + 3VDC
2 1 0 0 0 0 1 0 0 VDC2 = + 2VDC
1 0 0 0 1 0 0 1 0 VDC1 = + VDC
0 0 0 1 1 0 0 0 0 0
1 1 0 0 0 0 0 0
0 0 0 0 1 1 0 0
0 0 0 0 0 0 1 1
−1 0 0 1 0 0 0 0 1 −VDC1 = − VDC
−2 0 1 0 0 1 0 0 0 −VDC2 = −2VDC
−3 0 0 0 0 0 1 1 0 −VDC3 = − 3VDC
−4 0 0 1 0 0 1 0 0 −(VDC1 + VDC3) = − 4VDC
−5 0 1 0 0 0 0 1 0 −(VDC2 + VDC3) = − 5VDC
−6 0 1 1 0 0 0 0 0 −(VDC1 + VDC2 + VDC3) = − 6VDC
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For the laboratory verification, however, a specimen sevenlevel
asymmetric inverter is designed and tested. The detailed
operation of the reduced switch asymmetrical seven-level inverter
with two PV sources is demonstrated here. The proposed
asymmetrical seven-level inverter consist of four unidirectional
switches (T1, T2, T3 and T4) and two bi-directional switches (S1
and S2) as shown in Fig. 1b. The switches T1 and T4 will conduct
during the positive half cycle of the fundamental output voltage,
whereas, the switches T2 and T3 will conduct during the negative
half cycle. The bidirectional switches (S1 or S2 or both) as shown
in Fig. 1 will conduct to generate the voltage levels of magnitude
±VDC1, ±VDC2 and zero voltage as demonstrated in the switching
Table 2. The DC–DC converters connected with the respective PV
sources are working as a boost converter to increase the PV voltage
magnitude to the desired magnitude in such way that the ratio of
the two DC link voltage is always maintained as 1:2.
The switching states (S) and the ON/OFF status of the various
switches of the proposed seven-level inverter and the
corresponding generated voltage across the inverter output (Vab)
are given in Table 2. Further, to explain the operation of the
proposed inverter in details regarding the generation of seven
voltage levels, the power flow diagrams through the inverter
switches under various switching conditions (as given in Table 2)
are shown in Fig. 2. When the inverter switches, T1 and T4 are
ON, the output PV current flows through them towards the grid as
indicated by the arrow in Fig. 2a. The rest of the switches of the
inverter are remained OFF under this switching state as indicated
by faint line shown in Fig. 2a. The output inverter voltage, Vinv (or
Vab) during this period becomes 3VDC. Similarly, the operation of
the above seven-level inverter under the remaining switching
conditions can be explained by their power flow diagrams as
shown in Figs. 2b–h. The inverter output voltage can be made zero
by applying any one of the zero voltage switching conditions as
given in Table 2. The operation under zero voltage conditions have
also been depicted by the power flow diagrams as shown in
Figs. 2g and h.
3 Control of the proposed grid-tied asymmetrical
PV inverter
In this paper, the control of a grid-connected PV system for an
asymmetrical seven-level reduced switch inverter connected to two
unequal PV sources is developed and tested. The DC link voltages
of the proposed asymmetrical inverter are considered as the PV
sources of magnitudes VDC and 2VDC. A suitable control technique
has been adopted to maintain the grid current in sinusoidal nature,
having near unity power factor with the grid voltage. For doing
this, the individual DC link voltages should be maintained equal to
their DC link references (VDC1, VDC2), which is assumed to be in
the ratio of 1:2 in a variable irradiation conditions. Therefore, two
separate voltage controllers are used to maintain the over-all DC
link voltage as well as the individual DC link voltages of the
inverter. The design of the proposed grid-tied controller is to fulfil
the following aspects:
• To independently regulate the DC link voltages of the proposed
inverter with the ratio of 1:2 in such a manner that the maximum
power injected into the grid.
• The current injected to the grid should be sinusoidal in shape
and in phase with the grid voltage to maintain the unity power
factor.
In this paper, as the PV sources of different voltage ratings
(asymmetrical power rating) are used, that connected to the
inverter DC links through the individual DC–DC converter, the
separate MPPT can be used to obtain the DC link voltage of ratio
1:2 under different operating conditions. A perturbed and observed
based MPPT [30] is adopted to maximise the PV power that
generates the reference signals for the DC link voltage controllers
(VDC1, VDC2) as discussed in the following section:
(i) Control of total DC link voltage: To maintain the total DC link
voltage that is equal to a constant reference voltage corresponding
to an irradiation level, a closed-loop voltage controller is used as
shown in Fig. 3. To control the total DC link voltage, the sum of
the reference DC link voltages (VDC1* + VDC2) is compared with the total measured DC link capacitor voltages (VDC1 + VDC2) and the output error is processed through a proportional and integral (PI) controller. The gains of the PI-type voltage controller (Kp,1, Ki,1) should be tuned in such a way that, the magnitude of the reference current (Imax) injected into the grid becomes maximum for a grid-connected PV system. To track the frequency of the inverter current to the grid, a phase-locked loop is used to generate the sinusoidal reference grid current (Ig) for the grid current
controlled system as depicted in Fig. 3.
(ii) Control of grid current and grid voltage tracking: To maximise
the output current of the inverter (or the PV system), the reference
grid current (Ig) is compared with the measured value of grid current (Ig) and the current error is processed through a PI-type current controller. The gains of the current controller (Kp,c, Ki,c) are so tuned, that, the grid current becomes maximised and equal to the reference grid current (Ig). Under the steady-state condition, the
output of the current controller generates the reference signal
(VLf) that can be subtracted from the actual grid voltage (Vg) to generate the reference inverter voltage (Vref). This is called the grid tracker as the inverter reference voltage (or the inverter fundamental voltage) changes according to the variation of the grid voltage. If the grid voltage decreases, the difference (Vg − VLf)
reduces and hence the reference of the inverter (Vref) also
decreases. Thus, the inverter fundamental voltage always follows
the grid voltage. The output of the grid tracker is then properly
scaled down to generate the part of the reference voltage (Vref1) of
the proposed seven-level inverter.
(iii) Control of individual DC link voltages: For a seven-level
inverter with two unequal DC links voltages (VDC1, VDC2), their
ratio should be maintained as 1:2 under variable irradiation or
temperature conditions. When the total voltage controller maintains
the overall DC link voltage of the inverter to the summation of the
reference DC link voltages (equal to 3VDC), one more voltage
Table 2 Switching table of the proposed seven-level inverter with VDC1 = VDC and VDC2 = 2VDC
Switching states (S) Switching status (ON = 1, OFF = 0) Inverter output voltage, Vab
T1 T2 T3 T4 S1 S2
3 1 0 0 1 0 0 VDC1 + VDC2 = + 3VDC
2 1 0 0 0 0 1 VDC2 = + 2VDC
1 0 0 0 1 1 0 VDC1 = + VDC
0 0 0 1 1 0 0 0
1 1 0 0 0 0
0 0 0 0 1 1
−1 0 0 1 0 0 1 −VDC1 = −VDC
−2 0 1 0 0 1 0 −VDC2 = −2VDC
−3 0 1 1 0 0 0 −(VDC1 + VDC2) = −3VDC
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controller (individual voltage controller) is required to keep the
other DC link voltage VDC2 (equal to 2VDC) to be equal to the
reference voltage (VDC2*) as shown in Fig. 3. Hence, by using the
above two voltage controllers, the individual DC link voltages
(VDC1, VDC2) can be maintained at the desired reference values (1:2
voltage ratio). The output of the two voltage controllers multiplied
with grid frequency sine components that added to the grid voltage
(Vg) to obtain the reference signal of the inverter for implementing
the PWM signals as discussed in the next section.
However, when the irradiation between both the PV sources is
non-uniform, mismatch problem will arise leading to more losses
in the lower illuminated PV panel. To overcome such problem, the
arrangement of PV module is done in such a way that the whole
PV panel receives nearly uniform irradiation. The conventional
interconnection schemes which aim at enhancing power from
shaded PV array are series-parallel, total-cross-tied and bridgelinked
[33]. However, none of the configurations are effective in
reducing losses under wide shading conditions. In this proposed
work, a new PV module level arrangements, called ‘fixed
interconnection’ scheme [34] have been adopted, which may
equalise the shading effects among the PV modules and hence
maximises the PV power even under the hard shading condition. A
diode is connected across each of the PV modules for bypassing
Fig. 2 Power flow diagrams of the proposed seven-level inverter under different switching conditions with VDC1 = VDC and VDC2 = 2VDC
(a) T1 and T4 = ON, Vab = 3VDC, (b) T1 and S2 = ON, Vab = 2VDC, (c) S1 = ON, T4 = ON Vab = VDC, (d) S2 = ON, T3 = ON, Vab = −VDC, (e) S1 and T2 = ON, Vab = −2VDC, (f)
T2 and T3 = ON, Vab = −3VDC, (g) T3 and T4 = ON, Vab = 0, (h) T1 and T2 = ON, Vab = 0
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255
the current under shaded conditions as shown in Fig. 4. Here, the
PV panels are renumbered in such a way that the ratio of PV power
are always maintained in the ratio of 1:2 (same as DC link voltage
ratio) with equal amount of current. Fig. 4a shows the initial
arrangement of PV modules as PV1-1, PV1-2, PV1-3 for PV
source-1 and PV modules PV2-1, PV2-2, PV3-3, PV3-4, PV3-5,
PV3-6 for PV source-2. However, after adopting the ‘fixed
interconnection’ scheme, the modules are so arranged that, for any
shading pattern, the number of PV modules those are unshaded (or
shaded) are always in the ratio of 1:2, as depicted in Fig. 4b. Here,
the reconfiguration of proposed PV system with three different
shading conditions and corresponding PV connections are shown
in Figs. 4c–e. It is observed that, for each case, the number of PV
modules shaded (or unshaded) will be in the ratio of 1:2 for
balancing the maximum PV power generation from each PV
sources.
4 Pulse width modulation of the grid tied sevenlevel
inverter
For the proposed grid-connected MLI, a carrier-based level-shifted
PWM (LS-PWM) technique has been used in this paper to generate
the gate pulses of the inverter switches [35, 36]. To implement the
above PWM for the proposed seven-level inverter, six numbers of
high-frequency triangular carriers in the same phase, but are off-set
with their magnitudes (positive and negative offset) are compared
with the sinusoidal reference signal with frequency equal to the
grid frequency as shown in Fig. 5a. The reference of the grid-tied
inverter has been generated by the above grid controller as depicted
in Fig. 3.
With the variable weather and grid conditions, the magnitude of
the reference voltage (Am) will be controlled (remain synchronised
with the grid voltage) by controlling the modulation index (Ma).
The modulation index of the proposed asymmetrical MLI for a
fixed magnitude of the carriers (peak value of the summation of the
carriers, Ac) using the popular LS-PWM technique [35, 36] can be
represented as
Ma = Am
Ac
(1)
Fig. 5 also shows the switching states (S) for a seven-level inverter
generated by the LS-PWM. The switching states can be further
decoded as per Table 2 to generate the gate pulses for the switches
of the proposed seven-level inverter.
Fig. 3 Proposed grid-tied inverter control scheme
Fig. 4 Proposed 3 × 3 PV panel
(a) Initial interconnection of modules, (b) Fixed interconnection scheme with random arrangement of modules, (c) Shade dispersion with fixed interconnection scheme for shading in
first row, (d) Shading in third row, (e) Diagonally shading
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4.1 Calculation of inverter power losses and efficiency
The objective of the proposed MLI for a PV application is to
reduce the power losses and improve the system efficiency. The
power losses of the proposed generalised inverter due to
conduction and switching losses are therefore determined and the
expressions are applied to a specimen seven-level inverter.
4.1.1 Conduction losses: The instantaneous power dissipated in
a semiconductor switch in conduction period (conduction losses)
can be calculated by multiplying its on-state voltage drop Von(t)
and the magnitude of current I(t) carried by the device during the
turn-on period as
PCond(t) = Von(t) ⋅ I(t) (2)
The saturation voltage of the bidirectional switch used in the
proposed MLI (as given in Fig. 1) is the sum of the saturation
voltage of an IGBT and two diodes. The instantaneous conduction
losses, Pcon,B(t) due to the load current, I = ILsin (ωt) carried by the
bidirectional switch can be derived as
Pcond,B(t) = (VON,IGBT + 2VON,D)ILsin(ωt) + 2RD ⋅ IL 2 sin2(ωt)
+RT ⋅ IL
β + 1sinβ + 1(ωt)
(3)
where VON,IGBT, VON,D are the on-state voltage drop across IGBT
and anti-parallel diode, RT and RD are the equivalent resistance of
the IGBT and diode and β is a constant governed by the IGBT
characteristics. Similarly, the instantaneous conduction losses of
any unidirectional switches (IGBT/diode) used in the inverter can
be determined as
PCond,U (t) = (VON,IGBT + VON,D)ILsin(ωt) + RD ⋅ IL 2 sin2(ωt)
+RT ⋅ IL
β + 1sinβ + 1(ωt)
(4)
Thus, the instantaneous value of total conduction loss in the
proposed seven-level inverter can be expressed as
Pcond(t) = x(t)PCond,B(t) + y(t)PCond,U(t) (5)
where x(t), y(t) are the number of bidirectional and unidirectional
switches in the current path at any instant of time, whose value
mainly depends on the output voltage levels, nature of pulse
pattern, types of load (inductive, resistive or unity power factor
load etc.) and so on. From Table 2 as well as from the pulse pattern
shown in Figs. 5b and c, it is observed that in the proposed inverter,
two switches are in the current path at any time. It is observed from
Fig. 5b that, during the period of t0 to t1 and from t8 to t9, the two
bidirectional switches operate. Similarly, two unidirectional
switches will operate twice in a half cycle during the period of t3 to
t4 and t5 to t6. On the other hand, a combination of one
bidirectional switch and a unidirectional switches will operate four
times over the same half cycle for the period t1 to t2, t2 to t3, t4 to
t5, t6 to t7 and t7 to t8, respectively.
Hence, the expression of average conduction loss (PCOND) of
proposed seven-level inverter is calculated for a half-cycle as (see
(6))
4.1.2 Switching losses: To calculate the switching losses of the
proposed m-level inverter having four unidirectional switches and
(m − 1)/3 bidirectional switches, the power losses of each
unidirectional and bidirectional switches during on and off period
of the switches are calculated similar to [8]. The switching losses
Fig. 5 Waveforms of LS-PWM for a seven-level inverter
(a) Carriers, reference and switching states, (b) Simulation results of the gate pulses, (c) Corresponding experimental results of the gate pulses at a switching frequency of fs = 1.0
kHz
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mainly depends on the switching frequency of unidirectional
switches (fsu) and bidirectional switches (fsb) and their values can
be determined from the pulse patterns over one fundamental period
of the inverter switches as shown in Fig. 5b. From Fig. 5b it is
observed that, the switching frequency of the two unidirectional
switches, T1 and T2 are equal to the fundamental frequency (fo).
Thus, the total switching power losses of the proposed inverter can
be expressed as the sum of losses of both the unidirectional and
bidirectional switches as
PSW = Psw,U + Psw,B = Σi = 1
2 16
Vsu, iI ton + toff f o, i
+Σi = 2
4 16
Vsu, iI ton + toff f su, i
- Σj = 1
(m − 1)/3 16
Vsb, jI ton + toff f sb, j
(7)
where Vsu,i and Vsb,j are the blocking voltage of ith uni-directional
and jth bi-directional switch and fsu,i and fsb,j are the operating
frequency of the above uni-directional and bi-directional switch
and fo,i is fundamental switching frequency of the ith unidirectional
switches (T1 and T2). By assuming, I(ton + toff)/6 = α, a constant
for a specific rms load current (I) flowing through the IGBTs, the
above switching loss equation can be simplified as
PSW = αΣi = 1
2
Vsu, i f o, i + αΣi = 2
4
Vsu, i f su, i + α Σj = 1
(m − 1)/3
Vsb, j f sb, j (8)
For a proposed seven-level inverter, as the number of bidirectional
switches are two (S1 and S2) with their maximum blocking
voltages, Vsb,i = 2VDC and the number of unidirectional switches
are four (T1, T2, T3 and T4) with their blocking voltages are 3VDC.
Thus, the expression of the total approximated switching losses of
the proposed seven-level inverter can be simplified as
Psw = α 3VDCΣi = 1
2
f o, i + α 3VDCΣi = 3
4
f su, i + α 2VDCΣj = 1
2
f sb, i (9)
As the switching frequency of the two unidirectional switches, T1
and T2 are equal to the inverter fundamental frequency (fo), hence
the switching losses of T1 and T2 may be neglected. Further, it is
also observed from the pulse patterns of the inverter switches as
given in Fig. 4b that, for the inverter switching frequency fs of 1.0
kHz with fundamental inverter frequency fo of 50 Hz, the operating
frequency, fsu (or number of switching pulses) of unidirectional
switches, T3 and T4 are approximately fs/4 and of bidirectional
switches (fsb) are approximately fs/3, hence the overall switching
losses (Psw) of the inverter can be approximated as
Psw = α(3VDC × 2 f su) + α(2VDC × 2 f sb)
= 2αVDC(3 f su + 2 f sb) = 3αVDC f s
(10)
For an asymmetrical CHB MLI of a seven-level inverter requires
two H-bridges with DC link voltage ratio of 1:2, the expression of
switching losses of the inverter can be expressed using (7) as
4αVDCfs. By comparing the switching losses of the proposed sevenlevel
inverter (3αVDCfs) and the asymmetrical cascaded seven-level
inverter (4αVDCfs), it is observed that, the proposed MLI has 25%
less switching losses than that of the asymmetrical cascaded sevenlevel
inverter, as depicted in Fig. 6b.
4.1.3 Calculation of efficiency of the proposed inverter: For
the calculation of the proposed inverter efficiency, the parameters
of IGBTs (IGBTCT60AM-18F) and diodes (MUR1560G) used in
the experimental set up like their on-state conduction drop
(VON,IGBT, VON,D) and on-state resistance (RT, RD) and so on are
calculated from their data sheet. The values of on-state resistance
(RT, RD) can be obtained by drawing a straight line tangent to the
characteristic curves of the respective device. The resistance (RT,
RD) corresponds to the inverse slope of this line and on-state
voltage drop corresponds to that value of voltage for which the
current through them is zero in their characteristic curve [37]. The
parameters of the devices are calculated and are given in Table 3.
PCOND = 2
T ∫0
t1
2PCond,B(t) dt +∫t8
t9
2PCond,B(t) dt +∫t3
t4
2PCond,U(t) dt
+∫t5
t6
2PCond,U(t) dt +∫t1
t2
PCond,B(t) + PCond,U(t) dt
+∫t2
t3
(PCond,B(t) + PCond,U(t)) dt +∫t4
t5
PCond,B(t) + PCond,U(t) dt
+∫t6
t7
PCond,B(t) + PCond,U(t) dt +∫t7
t8
PCond,B(t) + PCond,U(t) dt
(6)
Fig. 6 Comparison of conduction power loss and switching power loss of the proposed inverter with other existing topologies at a switching frequency fs = 1
kHz for same parameters
(a) Conduction power loss, (b) Switching power loss
258 IET Renew. Power Gener., 2018, Vol. 12 Iss. 2, pp. 252-263
© The Institution of Engineering and Technology 2017
Moreover, for calculating the conduction losses, the operating
time of the different switches can also be calculated from the
simulated pulse pattern of inverter switches as given in Fig. 5b at a
specimen switching frequency of 1 kHz. On the basis of (4)–(6)
and the datasheet values given in Table 3, the value of average
conduction loss (PCOND) for the proposed seven-level inverter is
obtained as 11.21 W or 0.0125 p.u.
On the other hand, based on (7)–(9) and the values mentioned
in Table 3, the approximate value of the switching losses for the
proposed inverter at a switching frequency of 1.0 kHz is calculated
as 1.34 W or 0.0015 p.u. Thus, the overall conduction losses and
the switching losses of the proposed seven-level inverter is
calculated as 11.21 and 1.34 W for a 0.9 kW inverter output.
Hence, the overall efficiency of the proposed seven-level inverter is
calculated as 98.62%. However, with the increase of switching
frequency, the switching losses may increase proportionally, but
their conduction losses will remain constant. As the proposed gridtied
PV inverter switching frequency is chosen at 5 kHz, the
corresponding switching losses at 5 kHz switching frequency are
calculated as 6.7 W or 0.007 p.u. However, the conduction losses
remain same as 11.21 W. Hence, the efficiency of the proposed
inverter at actual switching frequency, fs = 5 kHz is calculated as
98.05% which is near to the experimental efficiency 97.90% of the
proposed inverter measured by the power analyser data.
Fig. 6 shows the comparison of conduction and switching losses
of the proposed converter for any voltage level (L) with the other
popular MLI configuration like asymmetrical CHB and a reduced
switch MLI [26]. It is observed from Fig. 6a that the proposed
topology has lower conduction losses compared with the others.
Also, Fig. 6b shows that the switching losses of the proposed
topology are lower than that of the other asymmetric topologies.
This is due to the reduced number of power switches conducting
simultaneously at any instant of time in the proposed inverter.
To elaborate the effectiveness of the proposed MLI further, a
comparative analysis of the proposed inverter over other MLI
configuration referred in this paper also have been done at 13
voltage levels and presented in Table 4. A generalised expression
of the number of inverter switches, DC voltage sources used have
been derived for few of the existing topologies used in the
references as presented in Table 4. From Table 4 it is observed that,
the proposed MLI configuration of 13-level inverter requires 8
switches as compared to 12 switches required by using the halfcascaded
topology [10], 9 switches in a cascaded MLI structured
[17] and 15 switches in hybrid-MLI [28] structure. From this
Table 4, it is also observed that the proposed reduced switch MLI is
better than most of the other MLI topologies in terms of the
number of DC voltage sources, amount of switching losses,
maximum voltage stress and efficiency.
5 Simulation and experimental results
The proposed reduced switch asymmetrical seven-level inverter is
simulated in Matlab/Simulink platform and the exhaustive
simulation results of the proposed inverter based grid-tied PV
system are presented here. For the simulation as well as laboratory
verification purposes, the rating of the PV system is taken as 0.9
kWp. The two PV stings of ratings 300 and 600 Wp are connected
to the inverter through the individual DC–DC converter to generate
the DC link voltages of ratio 1:2 for the asymmetrical inverter
under variable weather conditions. The values of voltage and
current controller gains (Kp,1, Kp,2, Ki,1) are assumed as 0.97, 0.48
and 0.091, respectively, for simulation as well as experimental
purposes. The details of the PV systems, converters and grid are
given in Table 5 in the Appendix. Fig. 7 shows the simulation
results of the DC link voltages or the output of the DC–DC boost
converters (VDC1, VDC2) and the corresponding DC link reference
voltages (VDC1, VDC2) for the asymmetrical reduced switch MLI.
It is observed from Fig. 7a that, the DC link voltages (VDC1, VDC2)
track the change in reference voltages (VDC1, VDC2) and their
ratio always maintained at the ratio 1:2 under variable irradiation.
Fig. 7b shows the change of inverter voltage (Vinv) and grid current
(Ig) with the change of DC link voltages due to the change of solar
irradiation. It is also observed from Fig. 7b that, the inverter
voltage levels remain constant even when the solar irradiance is
changed. The grid current controller also generates the sinusoidal
current whose magnitude is varying with the solar irradiation as
observed in Fig. 7c. The simulation results of the harmonic
spectrum of the grid current under a steady-state condition are
shown in Fig. 7d. It is observed from Fig. 7d that, except the
switching frequency components, the magnitudes of the other
harmonic components are very small and the THD of the grid
current (THDi) is only 1.53%.
The simulation results of inverter voltage (Vinv), grid voltage
(Vg) and the corresponding grid current (Ig) at steady state under
standard temperature and irradiation conditions (25°C, 1 kW/m2)
are shown in Fig. 8a. From Fig. 8a, it is observed that, the grid
current is sinusoidal in nature and very near to unity power factor.
The simulation of the proposed grid-tied system is also conducted
under fluctuating grid voltage. The simulation results of inverter
voltage and grid current for a 9% reduction of the grid voltage are
presented as in Fig. 8b. It is observed from Fig. 8b that, when the
grid voltage reduces, though the inverter voltage remains constant,
but the grid current (Ig) slightly increases due to the increase of the
voltage difference between the inverter and grid (Vinv − Vg).
To validate the performance of the proposed asymmetrical
reduced switch MLI for a grid-tied PV applications, a laboratory
prototype of a single-phase seven-level inverter is developed for a
0.9 kWp (at 300 Wp × 2, at 300 Wp) PV system connected to the
low-power residential grid. The switching frequency of the
proposed seven-level inverter for the grid-tied PV system is kept at
fs = 5 kHz for both simulation and experimental purposes. To
implement the PWM scheme and the whole grid control algorithm,
a d-SPACE (DS1103) based digital system is used due to its
availability in the laboratory. The parameters related to
experimental verification are given in Appendix (Tables 5 and 6).
The experimental results of DC link voltages of the inverter at
standard temperature and irradiation conditions (1000 W/m2) for
the PV sources are measured and presented in Fig. 9a. It is
observed from Fig. 9a that the DC link voltages of the inverters are
remained balance at the ratio of 1:2 for generating the desired
inverter voltage levels. However, for non-uniform irradiations of
the PV sources, the arrangements of the PV modules have been
done in such a way that nearly uniform irradiation can be received
by the PV systems.
Table 3a Parameters for IGBT (CT60AM-18F) and diode
(MUR1560G) based on their datasheet values
Parameters for the conduction loss calculation
on-state voltage drop of IGBT(VON,IGBT) and diode
(VON,D)
1.3 and 1.5 V
on-state resistance of IGBT (RT) and diode (RD) 0.11 and 0.01 Ω
maximum collector–emitter voltage 900 V
maximum collector current (Ic) 60 A
emitter current (Ie) 40 A
current gain of IGBT (β) Ic (Ic−Ie) = 3
Table 3b
Parameters for the switching loss calculation
turn-on (ton) and turn-off time of
switches (toff)
1.5 and 2 μs
forward current rating of IGBT (Imax) 60 A
blocking voltage of ith uni-directional
switch (Vsu,i) and jth bi-directional
switch (Vsb,j)
multiple DC link voltage
varying with inverter
configurations.
fundamental switching frequency (fo,i) 50 Hz
operating frequency of the
unidirectional (fsu,i) and bidirectional
switch (fsb,j)
depends on the inverter
switching frequency fs (1.0
kHz)
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259
Table 4 Comparative analysis between existing MLI and proposed asymmetrical MLI (for m-level inverter)
Inverter type Number of switches Optimum
number of DC
sources
Voltage stress Switching
power loss
Remarks
Unidirectional
switches
Bidirectional
switches
neutral point clamped
inverters [3]
2(m − 1) 0 (m − 1) medium in all the
switches
high capacitors balancing is a
problem
CHB MLI [6] 2(m − 1) 0 0.5(m − 1) low and equal in all
the switches
high requires isolated DC
supply
asymmetrical CHB
MLI [12]
4[log(m + 1/2)]/2 0 √m very high for high
voltage inverter
modules
low higher levels can be
attained with lesser
number of switches
improved double
flying capacitor
multicell converter [4]
(m − 1) 0 0.5(m − 1) high low bulky and expensive flying
capacitors are required
hybrid stacked MLI
with half-cascaded
configuration [10]
6 + 0.5(m − 1) 0 1 + 0.25(m − 1) less medium (i) all voltage levels cannot
be achieved (ii) a complex
control system is required
MLI [14] √(4m − 3) 0 0.5√(4m − 3)−1 less very low (i) isolated DC supply is
required (ii) high value of
THD
hybrid cascaded MLI
[28]
(m − 1) (m − 1)/4 0.5(m − 1) low medium asymmetrical configuration
is possible
switched series/
parallel sources
(SSPS)-based MLI
[15]
0.5(3m − 1) 0 0.5(m − 1) low high isolated DC supply is
required
MLI [17] 4 0.5(m − 3) 0.5(m − 1) very high in some
switches
low asymmetric configuration is
possible
proposed MLI 4 (m − 1)/3 [−1 + √(4m − 3)]/2 high on
unidirectional
switches
low (i) reduced no. of DC
voltage sources and
switches (ii) non-isolated
DC supply
Fig. 7 Simulation results of
(a) DC link voltages (VDC1, VDC2), (b) Inverter voltages, (c) Grid current at varying irradiance condition, (d) Harmonic spectrum of grid current
Table 5 Parameters for conducting simulation and experimental verification
Components Name of the parameters Values
inverters IGBT CT60AM-18F 900 V, 60 A
DC link voltage VDC1 = VDC 80 V
DC link voltage VDC2 = 2VDC 160 V
inverter output voltage, Vinv (or Vab) 240 V
inverter switching frequency (fs) 5 kHz
capacitor DC link capacitors (C1, C2) 400 μF, 800 μF
value of input capacitor (Cin1, Cin2) 66 μF, 100 μF
grid grid interfacing transformer (turns ratio 1:2) 3 kVA
grid voltage Vg (rms) 220 V
grid frequency, fo 50 Hz
DC–DC converter value of inductor (LS) 22.5 mH
switching frequency of DC–DC converter, Fsw 10 kHz
IGBT CT60AM-18F 900 V, 60 A
PV source-1 peak power rating (Wp) 300 W
total cells (Ns × Np) 72 × 1
PV source-2 peak power rating (Wp) 2 × 300 W
total cells (Ns × Np) (2 × 72) × 1
260 IET Renew. Power Gener., 2018, Vol. 12 Iss. 2, pp. 252-263
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In addition to this, by using the individual MPPT (MPPT1 and
MPPT2) along with independent DC–DC converter, the DC link
voltage can be balanced at the ratio of 1:2 using the individual
voltage control loops discussed in Section 3.
The experimental results of inverter voltage, grid current as
well as the harmonic spectrum of the grid current measured at the
standard irradiation condition (1000 W/m2) and at a lower
irradiation level (700 W/m2) are presented in Figs. 9b–e. It is
observed from Figs. 9b and d that the grid current is near sinusoidal
and in-phase with the inverter voltage. Figs. 9c and e show the
frequency spectrum of the grid current measuring up to 50th order
of harmonic components using Fluke 434 Power Quality Analyser.
It is also observed from the harmonic spectrum that the individual
harmonic components are very less (less than or around 1%) and
%THD of the line current are ≤2.2%. The experimental
arrangements for the proposed nine-level grid-connected PV
system are further presented as in Fig. 10.
6 Conclusion
This paper analyses the performance of the proposed reduced
switch asymmetrical MLI for a grid-connected PV system in terms
of losses and efficiency. It is observed that, the efficiency of the
proposed MLI is 97.90%. The performance of the proposed voltage
as well as the current controller for the unequal PV sources also
tested under standard irradiation conditions (1000 W/m2) as well as
variable irradiation. The simulation results of the DC link capacitor
voltages, inverter voltage and grid current under steady-state
Fig. 8 Simulation results of inverter output voltage (Vinv), grid voltage (Vg) and grid current (Ig) under
(a) Steady-state condition, (b) Fall of grid voltage (Vg reduced by 9%) condition
Fig. 9 Continued
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261
conditions as well as variable irradiation are analysed and
presented. The DC link voltage balancing of PV panels of unequal
power rating (voltage ratio of 1:2) is tested with uniform
irradiance. The simulation results of the above grid-tied system
under variable grid voltage are also analysed. It is observed that,
the variation of DC link capacitor voltage under variable irradiation
remain balanced. The simulation results of the proposed PV system
are experimentally verified with a specimen 0.9 kW grid-connected
PV system.
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8 Appendix
The parameters of the PV panels, DC–DC converters and grid-tied
PWM inverters for simulation and experimental verification are
given in Tables 5 and 6.
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